VLSIYOGI
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Setup and Hold
Calculator for Half cycle   [Desktop view only]

Constraints inputs: 
 

create_clock main_clk period period_value      -waveform {     }[ get_port main_clk]

_ _

set_clock_uncertainty -setup        [get_clocks main_clk ]

set_clock_uncertainty -hold          [get_clocks main_clk]

set_timing_derate  -early            -cell_delay

set_timing_derate  -late             -cell_delay       

CK

Q

DFF

CK

D

DFF

Launch clock path

Capture clock path

main_clk

Setup Slack   =
Hold Slack =   

__

__

Clock Skew = 

__

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